The present invention relates to methods for fabricating semiconductor memory devices and, more particularly, to methods for fabricating a semiconductor memory device using a ferroelectric film or a high dielectric constant film as a capacitor insulating film.
SRAMs (Static Random Access Memories) and DRAMs (Dynamic Random Access Memories) have been typical of randomly accessible memory devices. These memories are, however, both volatile. Moreover, the former memories, which require four to six transistor devices per memory cell, have limitations in advancement toward higher integration, while the latter memories, which need the periodical refresh of the capacitor for data holding, have a drawback of increased power consumption.
Under these circumstances, a so-called ferroelectric RAM (hereinafter, referred to as "FRAM") using a ferroelectric as a capacitor dielectric film is attracting attention as a randomly accessible nonvolatile memory device these days. Among others, an FRAM having a memory cell structure similar to the DRAM cell structure has been proposed in, for example, Japanese Patent Laid-Open Publication No. HEI 8-335673, in order to reduce the cell occupancy area.
FIG. 8 shows a memory cell of a conventional stacked type FRAM. This memory cell has a ferroelectric capacitor which includes a lower electrode 27 connected to one source/drain diffusion layer 24 of a MOS transistor, a capacitor ferroelectric film 28 formed on the lower electrode 27, and an upper electrode 31. The capacitor ferroelectric film 28 and the upper electrode 31 are in contact with each other at a top surface of the capacitor ferroelectric film 28. A bit line 33 is connected to the other source/drain diffusion layer 24 of the MOS transistor, a gate electrode 23 of the MOS transistor is connected to a word line, and the upper electrode 31 of the ferroelectric capacitor serves as a drive line. In FIG. 8, reference numeral 21 denotes a silicon substrate, 22 denotes a gate insulator, 25 denotes a first interlayer insulator, 26 denotes a contact plug, 29 denotes a diffusion inhibitor made of TiO.sub.2, 30 denotes an insulative thin film made of SiO.sub.2, and 32 denotes a second interlayer insulator.
Meanwhile, as the ferroelectric material, there have been proposed PbZr.sub.x Ti.sub.1-x O.sub.3 ("PZT"), and Bi (bismuth) layered structure materials, such as SrBi.sub.2 Ta.sub.2 O.sub.9 ("SBT"), which offers better fatigue characteristics and drivability at lower voltage than PZT. In order to educe the characteristics of these ferroelectric substances, however, a heat treatment process in an oxidizing atmosphere at high temperatures of 600-800.degree. C. as suggested in Japanese Patent Laid-open Publication No. HEI 10-4178 is needed.
However, during the formation of a ferroelectric by heat treatment in an oxidizing atmosphere as described above, particularly with SBT or the like that requires a high treatment temperature, the growth of crystal grains associated with film crystallization progresses relatively nonuniformly, causing the surface morphology of the film to deteriorate with a higher liability to the occurrence of surface irregularities. The deterioration of the film surface morphology or property may cause deterioration of ferroelectric characteristics such as increase in leak current and decrease in isolation voltage or withstand voltage of the ferroelectric film.
Also, in forming amicro capacitor, the uneven surface would lead to the decrease in precision of the capacitor area as well as in adhesion or contact between the ferroelectric film and the upper electrode. Therefore, attempts have been made to improve the surface property of the ferroelectric film by, for example, flattening a Pt lower electrode by electrolytic polishing, as described in Japanese Patent Laid-Open Publication No. HEI 10-189909. The flattening of the Pt lower electrode, however, has not provided a satisfactory solution because, however the lower Pt electrode is flattened, there occur surface irregularities or unevenness due to the grain growth of the ferroelectric film itself during the process of crystallization of the ferroelectric layer after the flattening of the lower Pt electrode. Furthermore, with the mere mechanical polishing such as described in the aforementioned Japanese Patent Laid-Open Publication HEI 10-4178, the ferroelectric film, which is a material vulnerable to mechanical damage and stress, would inevitably undergo considerable deterioration in ferroelectric characteristics, and besides tend to yield scratches. Thus, the mechanical polishing is unsuitable for semiconductor process.